Design of matrix-diagonal allocator for efficient network-on-chip routers
暂无分享,去创建一个
[1] A. Bouhraoua,et al. A simplified router architecture for the modified Fat Tree Network-on-Chip topology , 2009, 2009 NORCHIP.
[2] Chia Yee Ooi,et al. Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique , 2015, Int. J. Reconfigurable Comput..
[3] Venkatesan Muthukumar,et al. Loopback Virtual Channel Router Architecture for Network on Chip , 2012, 2012 Ninth International Conference on Information Technology - New Generations.
[4] Takahiro Watanabe,et al. A performance enhanced dual-switch Network-on-Chip architecture , 2015, ASP-DAC.
[5] A. Kumary,et al. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007 .