RCLK-VJ network reduction with Hurwitz polynomial approximation

We propose a new linear network reduction algorithm based on a generalized Y-Δ transformation technique in s-domain. Resultant admittance is kept as a rational function of s with a dramatically reduced order. Yet it preserves low-order terms of exact admittance evaluated with traditional symbolic analysis. Stability of transfer functions derived from reduced-order admittance is guaranteed via a Hurwitz polynomial approximation. Such low-order transfer functions are used in pole analysis and time domain waveform evaluation in response to any input signal.

[1]  Andrew T. Yang,et al.  Stable and efficient reduction of substrate model networks using congruence transforms , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  Hao Ji,et al.  How to efficiently capture on-chip inductance effects: introducing a new circuit element K , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  K. Kerns.  Accurate and stable reduction of RLC networks using split congurence transformations , 1996 .

[5]  Rui Wang,et al.  S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function , 1992, 30th ACM/IEEE Design Automation Conference.

[6]  Roland W. Freund,et al.  Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm , 1995, 32nd Design Automation Conference.

[7]  Ernest S. Kuh,et al.  Transient simulation of lossy interconnect , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[8]  Haifang Liao,et al.  Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Sung-Mo Kang,et al.  Performance driven MCM routing using a second order RLC tree delay model , 1993, 1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration.

[11]  Daniel Boley.  Krylov space methods on state-space control models , 1994 .

[12]  Hao Ji,et al.  KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect , 2001, ASP-DAC '01.

[13]  Shu-Park Chan,et al.  Introductory topological analysis of electrical networks , 1969 .

[14]  S. Akers.  The Use of Wye-Delta Transformations in Network Simplification , 1960 .

[15]  Joseph W. H. Liu,et al.  Modification of the minimum-degree algorithm by multiple elimination , 1985, TOMS.

[16]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, ICCAD 2001.

[17]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[18]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[19]  M. Yannakakis.  Computing the Minimum Fill-in is NP^Complete , 1981 .

[20]  Yehea I. Ismail,et al.  DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  J. Pasciak,et al.  Computer solution of large sparse positive definite systems , 1982 .

[22]  Sung-Mo Kang,et al.  Fast Approximation of the Transient Response of Lossy Transmission Line Trees , 1993, 30th ACM/IEEE Design Automation Conference.

[23]  Alan George,et al.  Computer Solution of Large Sparse Positive Definite , 1981 .

[24]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.