Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources

High temperature adversely impacts on reliability, performance, and leakage power of ICs. In behavioral synthesis, both resource usage allocation and resource binding influence the final thermal profile. Previous thermal-aware behavioral syntheses only focused on binding, ignoring allocation. This paper proposes thermal-aware behavioral synthesis with resource usage allocation. According to power density and feedbacks from thermal simulation, we allocate the number of resources under area constraint. Our flow effectively controls peak temperature and creates even power densities among resources of “different” and “same” types. Compared to classic behavioral synthesis of peak temperature control, our technique reduces peak temperature by 11.1 °C on average with no area overhead and only 1.2 more steps latency overhead.

[1]  Andrew V. Goldberg,et al.  An efficient implementation of a scaling minimum-cost flow algorithm , 1993, IPCO.

[2]  Min Ni,et al.  Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[3]  Alok Sharma,et al.  Empirical evaluation of some high-level synthesis scheduling heuristics , 1991, 28th ACM/IEEE Design Automation Conference.

[4]  Taewhan Kim,et al.  Thermal-aware high-level synthesis based on network flow method , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[5]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[6]  Li Shang,et al.  Adaptive Chip-Package Thermal Analysis for Synthesis and Design , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[7]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[8]  Sachin S. Sapatnekar,et al.  Placement of 3D ICs with Thermal and Interlayer Via Considerations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[9]  Li Shang,et al.  Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors , 2007, IEEE Micro.

[10]  Yuan Xie,et al.  Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design , 2006, J. VLSI Signal Process..

[11]  Seda Ogrenci Memik,et al.  Temperature-aware resource allocation and binding in high-level synthesis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[13]  Li Shang,et al.  Thermal crisis: challenges and potential solutions , 2006, IEEE Potentials.

[14]  Li Shang,et al.  Three-dimensional multiprocessor system-on-chip thermal optimization , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[15]  Seda Ogrenci Memik,et al.  Peak temperature control and leakage reduction during binding in high level synthesis , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[16]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[17]  Gang Wang,et al.  Design space exploration using time and resource duality with the ant colony optimization , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[18]  Massoud Pedram,et al.  Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.

[19]  Mahmut T. Kandemir,et al.  Thermal-aware task allocation and scheduling for embedded systems , 2005, Design, Automation and Test in Europe.

[20]  Li Shang,et al.  TAPHS: thermal-aware unified physical-level and high-level synthesis , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[21]  Seda Ogrenci Memik,et al.  An Integrated Approach to Thermal Management in High-Level Synthesis , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.