Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis

Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance. ur results show that WCET estimates of applications running on top of probabilistic wNoCs are reduced by 40% and 75% on average for 4x4 and 6x6 wNoC setups respectively when compared against deterministic wNoCs.

[1]  Francisco J. Cazorla,et al.  A cache design for probabilistically analysable real-time systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Anne Marsden,et al.  International Organization for Standardization , 2014 .

[3]  Sunggu Lee Real-time wormhole channels , 2003, J. Parallel Distributed Comput..

[4]  Tullio Vardanega,et al.  ON THE INDUSTRIAL FITNESS OF WCET ANALYSIS , 2011 .

[5]  Tullio Vardanega,et al.  Fitting processor architectures for measurement-based probabilistic timing analysis , 2016, Microprocess. Microsystems.

[6]  Francisco J. Cazorla,et al.  pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems , 2016, 2016 Euromicro Conference on Digital System Design (DSD).

[7]  Francisco J. Cazorla,et al.  Bus designs for time-probabilistic multicore processors , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  S. Nadarajah,et al.  Extreme Value Distributions: Theory and Applications , 2000 .

[9]  Francisco J. Cazorla,et al.  Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems , 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[10]  Mithuna Thottethodi,et al.  Self-tuned congestion control for multiprocessor networks , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[11]  Computing Accurate Performance Bounds for Best Effort Networks-on-Chip , 2013, IEEE Transactions on Computers.

[12]  Liliana Cucu-Grosjean,et al.  Timing analysis of an avionics case study on complex hardware/software platforms , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[14]  Thomas M. Conte,et al.  A Benchmark Characterization of the EEMBC Benchmark Suite , 2009, IEEE Micro.

[15]  Francisco J. Cazorla,et al.  Enabling TDMA Arbitration in the Context of MBPTA , 2015, 2015 Euromicro Conference on Digital System Design.

[16]  George Lima,et al.  Extreme Value Theory for Estimating Task Execution Time Bounds: A Careful Look , 2016, 2016 28th Euromicro Conference on Real-Time Systems (ECRTS).

[17]  Francisco J. Cazorla,et al.  Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation , 2017, ACM Trans. Design Autom. Electr. Syst..

[18]  Jean-Yves Le Boudec,et al.  Network Calculus: A Theory of Deterministic Queuing Systems for the Internet , 2001 .

[19]  Francisco J. Cazorla,et al.  Improving performance guarantees in wormhole mesh NoC designs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Iain Bate,et al.  Achieving Appropriate Test Coverage for Reliable Measurement-Based Timing Analysis , 2016, 2016 28th Euromicro Conference on Real-Time Systems (ECRTS).

[21]  Tullio Vardanega,et al.  On uses of extreme value theory fit for industrial-quality WCET analysis , 2017, 2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES).

[22]  Alan Burns,et al.  Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).