On test generation for transition faults with minimized peak power dissipation

This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.

[1]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[3]  William J. Cook,et al.  Combinatorial optimization , 1997 .

[4]  B. I. Devadas,et al.  Design for testability : Using scanpath techniques for path-delay test and measurement , 1991 .

[5]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[6]  B.I. Dervisoglu,et al.  DESIGN FOR TESTABILITY USING SCANPATH TECHNIQUES FOR PATH-DELAY TEST AND MEASUREMENT , 1991, 1991, Proceedings. International Test Conference.

[7]  Michael S. Hsiao,et al.  Novel ATPG algorithms for transition faults , 2002, Proceedings The Seventh IEEE European Test Workshop.

[8]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[9]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[10]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 2000, J. Electron. Test..

[12]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[13]  Irith Pomeranz,et al.  Forward-looking fault simulation for improved static compaction , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Irith Pomeranz,et al.  Static compaction for two-pattern test sets , 1995, Proceedings of the Fourth Asian Test Symposium.

[15]  Srinivas Patil,et al.  Scan-based transition test , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Irith Pomeranz,et al.  On n-detection test sets and variable n-detection test sets for transition faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[18]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  N. K. Jha,et al.  Testing of Digital Systems: Delay fault testing , 2003 .