A high speed, low power PRML read channel device

A complete read channel device using PR-IV signalling and maximum likelihood detection is described. Descriptions, simulated performance and measured results of the digital adaptive feedback loops (AGC, FIR tap weights, DFE tap weights, frequency and phase) in the read channel are presented. Analog FIR filter and hash A/D converter performance is presented. The weighted averaging servo demodulation technique used in the device is described and compared to integration. This monolithic CMOS device consumes less than 0.75 W when reading at 85 Mbps, and occupies a step-and-repeat area of 24.6 mm/sup 2/. >

[1]  Roy D. Cideciyan,et al.  A PRML System for Digital Magnetic Recording , 1992, IEEE J. Sel. Areas Commun..

[2]  Trent Dudley,et al.  A digital read/write channel with EEPR4 detection , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[3]  R. L. Galbraith,et al.  INTEGRATING A PARTIAL RESPONSE MAXIMUM LIKELIHOOD DATA CHANNEL INTO THE IBM 0681 DISK DRIVE , 1990, 1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990..

[4]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[5]  D. Browning,et al.  A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[6]  Roger W. Wood,et al.  Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel , 1986, IEEE Trans. Commun..