BEHAVIORAL FAULT SIMULATION

Due to the ever-increasing complexity of VLSI circuits, the use of VHDL [Vhd87] behavioral descriptions in the fields of test generation and fault simulation becomes advised. In order to understand this evolution and the context in which it is efficient, the increasing complexity of VLSI circuits must be considered. To better cope with the complexity of existing and future systems, higher abstraction levels must be taken into account. Furthermore, the only knowledge about the device being tested may come from data sheets or signal measurements. In this case the only way to generate test patterns is behavioral testing. Today, such a task is done manually and one of the main interests in Behavioral Test Pattern Generation (BTPG) is to automate it. Another point to consider is that the test generation process is an integral part of the design process and its implementation must begin during the behavioral design phase.

[1]  Jacob A. Abraham,et al.  Structured Functional Level Test Generation Using Binary Decision Diagrams , 1986, ITC.

[2]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Jean François Santucci,et al.  Pseudo-random behavioral ATPG , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[4]  Jean François Santucci,et al.  A methodology to reduce the computational cost of behavioral test pattern generation , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[5]  Anas N. Al-Rabadi,et al.  A comparison of modified reconstructability analysis and Ashenhurst‐Curtis decomposition of Boolean functions , 2004 .

[6]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[7]  Jean François Santucci,et al.  Speed up of Behavioral A.T.P.G. Using a Heuristic Criterion , 1993, 30th ACM/IEEE Design Automation Conference.

[8]  Daniel P. Siewiorek,et al.  Functional Testing of Digital Systems , 1983, 20th Design Automation Conference Proceedings.

[9]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[10]  Daniel G. Saab,et al.  Beta: behavioral testability analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[11]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[12]  Magdy S. Abadir,et al.  Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams , 1985, International Test Conference.

[13]  H. D. Hümmer,et al.  Functional Tests for Hardware Derived from VHDL Description , 1991 .

[14]  Sumit Ghosh,et al.  On behavior fault modeling for digital designs , 1991, J. Electron. Test..

[15]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  P. David Stotts,et al.  Hierarchical Modeling of Software Systems with Timed Petri Nets , 1985, PNPM.

[17]  Daniel P. Siewiorek,et al.  A Methodology for the Rapid Injection of Transient Hardware Errors , 1996, IEEE Trans. Computers.

[18]  James Lyle Peterson,et al.  Petri net theory and the modeling of systems , 1981 .

[19]  F. E. Norrod,et al.  An Automatic Test Generation Algorithm for Hardware Description Languages , 1989, 26th ACM/IEEE Design Automation Conference.