Classical floorplanning harmful?

Classical floorplanning formulations may lead researchers to solve the wrong problems. This paper points out several examples, including (i) the preoccupation with packing-driven, as opposed to connectivity-driven, problem formulations and benchmarking standards; (ii) the preoccupation with rectangular (and L or T shaped) block shapes; and (iii) the lack of attention to algorithm scalability, fixed-die layout requirements, and the overall RTL-down methodology context. The right problem formulations must match the purpose and context of prevailing RTL-down design methodologies, and must be neither overconstrained nor underconstrained. The right solution ingredients are those which are scalable while delivering good solution quality according to relevant metrics. We also describe new problem formulations and solution ingredients, notably a perfect rectilinear floorplanning formulation that seeks zero-whitespace, perfectly packed rectilinear floorplans in a fixed-die regime. The paper closes with a list of questions for future research.

[1]  Charles R. Giardina,et al.  Elliptic Fourier features of a closed contour , 1982, Comput. Graph. Image Process..

[2]  H. Murata,et al.  Rectangle-packing-based module placement , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  Xianlong Hong,et al.  Timing-driven floor-planning algorithm for building block layout , 1996, Other Conferences.

[4]  Toshimitsu Masuzawa,et al.  A layout adjustment problem for disjoint rectangles preserving orthogonal order , 2002, Systems and Computers in Japan.

[5]  Takashi Kambe,et al.  Rectilinear Shape Formation Method on Block Placement , 1998 .

[6]  Dmitry Chetverikov,et al.  A multiresolution algorithm for rotation-invariant matching of planar shapes , 1992, Pattern Recognit. Lett..

[7]  John Grason,et al.  Methods for the computer-implemented solution of a class of "floorplan , 1970 .

[8]  Sartaj Sahni,et al.  Optimal realizations of floorplans [VLSI layout] , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Anna Pagh,et al.  Linear-Time Heuristics for Minimum Weight Rectangulation (Extended Abstract) , 1996, SWAT.

[10]  K. Saraswat,et al.  Interconnect performance modeling for 3D integrated circuits with multiple Si layers , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[11]  Jimmy J. M. Tan,et al.  Minimum rectangular partition problem for simple rectilinear polygons , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Shin'ichi Wakabayashi,et al.  Hierarchical floorplanning and detailed global routing with routing-based partitioning , 1990, IEEE International Symposium on Circuits and Systems.

[13]  Ernest S. Kuh,et al.  Design space exploration using the genetic algorithm , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[14]  Michael Ian Shamos,et al.  Computational geometry: an introduction , 1985 .

[15]  T. C. Hu.  Physical design: mathematical models and methods , 1997, ISPD '97.

[16]  Youn-Long Lin,et al.  Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy , 1998, ISPD '98.

[17]  Christos Levcopoulos.  Fast heuristics for minimum length rectangular partitions of polygons , 1986, SCG '86.

[18]  D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.

[19]  Mark S. Boddy,et al.  Solving Time-Dependent Planning Problems , 1989, IJCAI.

[20]  Rama Chellappa,et al.  Classification of Partial 2-D Shapes Using Fourier Descriptors , 1987, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[21]  Henk J. A. M. Heijmans,et al.  Similarity and Symmetry Measures for Convex Shapes Using Minkowski Addition , 1998, IEEE Trans. Pattern Anal. Mach. Intell..

[22]  Martin D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD '94.

[23]  Helmut Alt,et al.  Approximate matching of polygonal shapes , 1995, SCG '91.

[24]  Chung-Kuan Cheng,et al.  A network flow approach for hierarchical tree partitioning , 1997, DAC.

[25]  Majid Sarrafzadeh,et al.  Nostradamus: a floorplanner of uncertain design , 1998, ISPD '98.

[26]  Robert W. Dutton,et al.  An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks , 1985, 22nd ACM/IEEE Design Automation Conference.

[27]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[28]  Esther M. Arkin,et al.  An efficiently computable metric for comparing polygonal shapes , 1991, SODA '90.

[29]  Youn-Long Lin,et al.  A timing-driven soft-macro resynthesis method in interaction with chip floorplanning , 1999, DAC '99.

[30]  Majid Sarrafzadeh,et al.  Nostradamus: a floorplanner of uncertain designs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Helmut Alt,et al.  Approximate Matching of Polygonal Shapes (Extended Abstract) , 1991, SCG.

[32]  Takashi Kambe,et al.  Hybrid floorplanning based on partial clustering and module restructuring , 1996, ICCAD 1996.

[33]  I. Koren,et al.  Optimal aspect ratios of building blocks in VLSI , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[34]  Hidetoshi Onodera,et al.  Branch-and-bound placement for building block layout , 1991, 28th ACM/IEEE Design Automation Conference.

[35]  Farzin Mokhtarian,et al.  Scale-Based Description and Recognition of Planar Curves and Two-Dimensional Shapes , 1986, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[36]  Daniel P. Huttenlocher,et al.  Comparing Images Using the Hausdorff Distance , 1993, IEEE Trans. Pattern Anal. Mach. Intell..

[37]  Yavuz A. Bozer,et al.  An improvement-type layout algorithm for single and multiple-floor facilities , 1994 .

[38]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, ICCAD 1996.

[39]  Teofilo F. Gonzalez,et al.  On the generalized channel definition problem , 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

[40]  Christos H. Papadimitriou,et al.  On the Optimal Bisection of a Polygon , 1992, INFORMS J. Comput..

[41]  Youn-Long Lin,et al.  Preserving HDL synthesis hierarchy for cell placement , 1997, ISPD '97.

[42]  Gabriele Saucier,et al.  A hierarchy-driven FPGA partitioning method , 1997, DAC.

[43]  Thomas Lengauer,et al.  Robust and accurate hierarchical floorplanning with integrated global wiring , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[44]  Helmut Alt,et al.  Measuring the resemblance of polygonal curves , 1992, SCG '92.

[45]  Larry J. Stockmeyer,et al.  Optimal Orientations of Cells in Slicing Floorplan Designs , 1984, Inf. Control..

[46]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[47]  Tyng-Luh Liu,et al.  Approximate tree matching and shape similarity , 1999, Proceedings of the Seventh IEEE International Conference on Computer Vision.

[48]  Kia Bazargan.  A floorplanner of uncertain designs , 1997 .

[49]  J. Grason.  Methods for the computer-implemented solution of a class of 'floor plan' design problems , 1970 .

[50]  Tsu-Chang Lee,et al.  A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules , 1993, 30th ACM/IEEE Design Automation Conference.

[51]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[52]  Evangeline F. Y. Young,et al.  How good are slicing floorplans? , 1997, Integr..

[53]  R. H. J. M. Otten,et al.  Graphs in floor‐plan design , 1988 .

[54]  M. Sarrafzadeh,et al.  An integrated algorithm for optimal floorplan sizing and enumeration , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[55]  Bernard Chazelle.  Triangulating a simple polygon in linear time , 1991, Discret. Comput. Geom..

[56]  Ting-Chi Wang,et al.  Optimal floorplan area optimization , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[57]  Ernest S. Kuh,et al.  Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.