Stochastic Logical Effort : Designing for Timing Yield on the Back of an Envelope

As we move into the nano era in integrated circuit fabrication technologies, the performance variability due to statistical process variations and environmental fluctuations is becoming more and more significant. Considerable effort has been expended in the EDA community during the past several years in trying to cope with the so-called statistical timing problem. However, most of this effort has been aimed at generalizing the static timing analyzers to the statistical case in an EDA tool centric manner. In this paper, we take a pragmatic, design centric approach in pursuit of a simple yet powerful stochastic gate delay model that can be used to develop a very efficient timing yield estimation methodology, and that can enable tractable timing yield optimization and eventually lead to simple yet meaningful and useful design guidelines. In doing so, we first develop a generalization of the logical effort delay model for the stochastic case. In the spirit of the standard logical effort formalism, the stochastic gate delay model we propose separates the characterization of statistical variability from the gate topology, type, size and loading information. We then demonstrate why and how the simple stochastic gate delay model that features this separation of concerns can be used as a very powerful tool in timing yield estimation and yield optimization. We develop an extremely efficient and simple methodology for optimal gate sizing in order to maximize the timing yield of a path. Using this methodology, we analyze several cases of practical importance and arrive at meaningful and practical conclusions on optimal gate sizing. When only inter-die variations are considered, we show that the sizing that minimizes the nominal path delay also maximizes the path timing yield. However, we also show that this does not hold in general, especially when local, intra-die statistical variations are significant. The simple stochastic gate delay model proposed in this paper can be effectively used to guide the generation and selection of sample points in the parameter/probability space in a transistor-level simulation based Monte Carlo method for timing yield estimation. We discuss in a companion paper how transistor-level Monte Carlo analysis can be accelerated using novel importance sampling and other variance reduction