Interfacial Delamination Near Solder Bumps and UBM in Flip-Chip Packages

Using detailed finite element models, a fracture analysis of solder bumps and under bump metallurgy (UBM) in flip-chip packages is carried out. Our objective is to identify likely fracture modes and potential delamination sites at or near these microstructural components. In order to study flip-chips, whose dimension spans from sub-micron thickness UBM layers to several millimeters wide package, we have applied a multi-scale finite element analysis (MS-FEA) procedure. In this procedure, initially, deformation of whole thermally loaded package is analyzed. Then, the results are prescribed as the boundary conditions in a very detailed cell model, containing a single solder bump, to investigate micro-deformation surrounding UBM. Using the models with two different scales, accurate stress fields as well as fracture parameters of various interface cracks can be determined. The MS-FEA is ideally suited for the flip-chip packages since they contain many identical solder bumps. A cell model can be repeatedly used to probe stress and fracture behaviors at different locations. The computed results show high stress concentrations near the corners of solder bumps and UBM layers. Based on the energy release rate calculations, solder bumps located near the edge of chip are more likely to fail. However, our results also suggest possible delamination growth at solder bumps near the center of chip. In addition, we have observed increasing energy release rates for longer cracks, which implies a possibility of unstable crack growth. @DOI: 10.1115/1.1348338#

[1]  Sergey V Shkarayev,et al.  Thermo-mechanical stresses for a triple junction of dissimilar materials: Global-local finite element analysis , 1998 .

[2]  S. Wiegele,et al.  Reliability and process characterization of electroless Nickel-Gold/Solder flip chip interconnect technology , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[3]  J. Lau,et al.  Thermal fatigue life prediction of flip chip solder joints by fracture mechanics method , 1993 .

[4]  A. G. Evans,et al.  An experimental study of the fracture resistance of bimaterial interfaces , 1989 .

[5]  Toshio Nakamura,et al.  Computational analysis of dynamic crack propagation along a bimaterial interface , 1994 .

[6]  Sheng Liu,et al.  Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique , 1998 .

[7]  T. E. Wong,et al.  Development of BGA solder joint vibration fatigue life prediction model , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[8]  S. Rzepka,et al.  The effect of underfill imperfections on the reliability of flip chip modules: FEM simulations and experiments , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[9]  Sergey V Shkarayev,et al.  Global/local finite element analysis for singular stress fields near the junction of dissimilar elastic and elastic-plastic materials in electronic packages , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[10]  J.J. Shea,et al.  Electronic packaging materials and their properties , 2001, IEEE Electrical Insulation Magazine.

[11]  Jianmin Qu,et al.  Delamination cracking in encapsulated flip chips , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[12]  S. Rzepka,et al.  The Effect of Underfill and Underfill Delamination on the Thermal Stress in Flip-Chip Solder Joints , 1998 .

[13]  Sergey V Shkarayev,et al.  Potential Failure Sites in a Flip-Chip Package With and Without Underfill , 1997, Application of Fracture Mechanics in Electronic Packaging.