A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop

A low-power high-data-rate ASK IF receiver is proposed. It consists of one digital-control automatic-gain-control (AGC) loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of the programmable-gain amplifier (PGA) in the AGC loop is discretely adjusted by a gain-control block to eliminate the multidigit analog-to-digital converter. Due to the high sensitivity of the ASK detector, a large controllable input range can be obtained in the AGC loop. The ASK IF receiver has been implemented in 0.18-μm CMOS, and the overall current consumption is 1.21 mA with a supply voltage of 1.8 V. The ASK receiver achieves a 2-Mb/s data rate with an IF carrier frequency of 10 MHz, and an input signal amplitude ranges from 180 μV to 900 mV.

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