Efficient verification of sequential circuits on a parallel system

The paper presents a method to verify functional correctness of FSMs on a parallel system. The equivalence condition is expressed in theoretical terms within the framework of the product machine. It consists in proving that a set of states of the product machine is unreachable from the initial reset state. The algorithm is based on state-of-the-art simulation techniques for explicit enumeration on the inputs and is implemented on a parallel machine. The states of the product machine are partitioned for evaluation among available processors. Experimental results show that the method is applicable to real-world circuits and that the parallel version achieves an almost linear speedup in the number of processors.<<ETX>>

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Wayne H. Wolf,et al.  The FSM network model for behavioral synthesis of control-dominated machines , 1990, 27th ACM/IEEE Design Automation Conference.

[3]  Srinivas Patil,et al.  A parallel branch and bound algorithm for test generation , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Edward J. McCluskey,et al.  Derivation of optimum test sequences for sequential machines , 1964, SWCT.

[5]  Paolo Prinetto,et al.  Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis , 1989, IFIP Congress.

[6]  Thomas Filkorn.  A Method for Symbolic Verification of Synchronous Circuits , 1991 .

[7]  A. Richard Newton,et al.  An efficient verifier for finite state machines , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[9]  Michael J. Quinn,et al.  Parallel graph algorithms , 1984, CSUR.

[10]  Srinivas Devadas,et al.  On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[12]  Alberto L. Sangiovanni-Vincentelli,et al.  Logic Verification Algorithms and their Parallel Implementation , 1987, 24th ACM/IEEE Design Automation Conference.

[13]  Paolo Prinetto,et al.  Proving finite state machines correct with an automaton-based method , 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

[14]  Seung-Ho Hwang,et al.  An Efficient Design Correctness Checker of Finite-State Machines , 1987 .

[15]  Paolo Prinetto,et al.  Formal verification of hardware correctness: introduction and survey of current research , 1988, Computer.

[16]  Paolo Prinetto,et al.  The Product Machine and Implicit Enumeration to prove FSMs correct , 1991 .

[17]  Seh-Woong Jeong,et al.  ATPG aspects of FSM verification , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.