FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT

Fast Fourier transform (FFT) is one of the fundamental processing block used in many signal processing applications (i.e. for orthogonal frequency division multiplexing in wireless telecommunication). Therefore, every proposal to reduced latency, resources or accuracy errors of FFT implementation counts. This paper proposes the implementation of the butterfly processing elements (BPE) where the concept of the radix-r butterfly computation has been formulated as the combination of α radix-2 butterflies implemented in parallel. An efficient FFT implementation is feasible using our proposed multiplexed and pipelined BPE. Compared to a state-of-the-art reference based on pipelined and parallel structure FFTs, and FPGA based implementation reveals that the maximum throughput is improved by a factor of 1.3 for a 256-point FFT and reach a throughput of 2680 MSps on Virtex-7. The analysis extends to touch on key performance measurements metrics such as throughput, latency and resource utilization.