Advanced Simulation for ESD Protection Elements

Electrostatic discharge (ESD) failure is one of the most important causes of reliability problems, therefore the design and optimization of ESD devices have to be done. To achieve very short time to market and reduce the development effort, one tries to make use of the benefit of simulation tools. However, due to the complex physical mechanism of ESD events and the hard mathematic calculation in the snapback region, simulation of the I-V characteristic of ESD protection devices has been proved to be difficult. This chapter aims at providing a systematic way to ESD simulation, including the process simulation, device simulation and circuit level simulation. Process/device simulation offers an effective way to evaluate the performance of ESD protection structures. However, to prevent the injury of ESD, protection circuits are used sometimes. Therefore circuit level simulation is needed. There are several process/device simulation tools in the world, the most widely used of which include Tsuprem4/Medici, Athena/Atlas and Dios/Mdraw/Dessis. Tsuprem4, Athena and Dios are process simulators, while Medici, Atlas and Dessis are device simulators. Mdraw is an independent mesh optimization tool, and the similar functions are integrated in device simulation tools, such as Medici and Atlas. The process and device simulation methods introduced in the following will be based on Dios/Mdraw/Dessis, except for the mixed-mode simulation, which is based on Tsuprem4/Medici. And the circuit level simulation will be carried out on the Candence platform.

[1]  Jung-Hoon Chun,et al.  Investigation of thermal breakdown mechanism in 0. 13 /spl mu/m technology ggNMOS under ESD conditions , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[2]  B. Deutschmann,et al.  Using device simulations to optimize ESD protection circuits , 2004, 2004 International Symposium on Electromagnetic Compatibility (IEEE Cat. No.04CH37559).

[3]  J.J. Liou,et al.  TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications , 2007, IEEE Transactions on Electron Devices.

[4]  Bin Li,et al.  An ESD Protection Device Simulation-Design Methodology based on MEDICI , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[5]  Yang Xing,et al.  Simulation models of ESD event in ICs , 2001, 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443).

[6]  Jeremy C. Smith,et al.  A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[7]  Qiong Wu,et al.  Mixed-mode ESD protection circuit simulation-design methodology , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[8]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[9]  W. Fichtner,et al.  Characterization and optimization of a bipolar ESD-device by measurements and simulations , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[10]  N. Nolhier,et al.  TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices , 2006, IEEE Transactions on Device and Materials Reliability.

[11]  Harald Gossner,et al.  Advanced simulation methods for ESD protection development , 2003 .

[12]  Beatrice Gralton,et al.  Washington DC - USA , 2008 .

[13]  P. Perdu,et al.  TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology , 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

[14]  P. Perdu,et al.  TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology , 2003, Microelectron. Reliab..

[15]  Chih-Yao Huang,et al.  Simulation prediction of electrothermal behaviors of ESD N/PMOS devices , 2005 .

[16]  Yan Han,et al.  Robustness evaluation of ESD protection devices in NEMS using a novel TCAD methodology , 2008, 2008 3rd IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

[17]  A. Amerasekera,et al.  Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .

[18]  Ming-Dou Ker,et al.  Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test , 2008, IEEE Journal of Solid-State Circuits.

[19]  N. Nolhier,et al.  Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[20]  S. Voldman,et al.  A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[21]  M. Sachdev,et al.  A transient power supply ESD clamp with CMOS thyristor delay element , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[22]  W. Fichtner,et al.  TCAD software for ESD on-chip protection design , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[23]  Kai Esmark Device simulation of ESD protection elements , 2001 .

[24]  Cynthia A. Torres,et al.  Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[25]  Markus Paul Josef Mergens On-chip ESD protection in integrated circuits , 2001 .

[26]  A. Amerasekera,et al.  Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[27]  Albert Wang,et al.  A study of NMOS behavior under ESD stress: simulation and characterization , 1998 .

[28]  Haigang Feng,et al.  A mixed-mode ESD protection circuit simulation-design methodology , 2003 .

[29]  A. Amerasekera,et al.  Prediction of ESD robustness in a process using 2D device simulations , 1993, 31st Annual Proceedings Reliability Physics 1993.