Near-threshold-voltage circuit design: The design challenges and chances

NTV is a new low power design concept for the pursuit of the highest power usage efficiency. The characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. The circuit/architecture design policy under NTV is also different from its normal supply voltage operation. Process variation, performance degradation, and noise-interference are the three major design challenges in NTV design. In this paper, some effective candidate design solutions are presented to overcome these crucial NTV issues.

[1]  John Keane,et al.  Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Naresh R. Shanbhag,et al.  Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  I-Chyn Wey,et al.  Reliable and low error dual modular redundancy FIR filter with wide protection window , 2014, IEICE Electron. Express.

[5]  I-Chyn Wey,et al.  Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits , 2014, Integr..

[6]  Sanu Mathew,et al.  A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS , 2013, IEEE Journal of Solid-State Circuits.

[7]  An-Yeu Wu,et al.  A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[8]  Massoud Pedram,et al.  A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[9]  K. Kameswar Reddy,et al.  Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy Block , 2015 .

[10]  David Blaauw,et al.  A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[11]  Yu-Sheng Yang,et al.  A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design , 2014, Microelectron. J..

[12]  P. Corsonello,et al.  High-performance noise-tolerant circuit techniques for CMOS dynamic logic , 2008, IET Circuits Devices Syst..

[13]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[14]  Joseph L. Mundy,et al.  Optimizing noise-immune nanoscale circuits using principles of Markov random fields , 2006, GLSVLSI '06.

[15]  Kaushik Roy,et al.  ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Gu-Yeon Wei,et al.  Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency , 2009, IEEE Micro.

[17]  Kaushik Roy,et al.  Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation , 2010, IEEE Journal of Solid-State Circuits.

[18]  Farshad Moradi,et al.  New subthreshold concepts in 65nm CMOS technology , 2009, 2009 10th International Symposium on Quality Electronic Design.

[19]  David Blaauw,et al.  Soft-edge flip-flops for improved timing yield: design and optimization , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[20]  Joseph L. Mundy,et al.  Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[21]  David Blaauw,et al.  Energy-Efficient Subthreshold Processor Design , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  An-Yeu Wu,et al.  Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[24]  Bo Zhai,et al.  Exploring Variability and Performance in a Sub-200-mV Processor , 2008, IEEE Journal of Solid-State Circuits.

[25]  Yiannos Manoli,et al.  A 62 mV 0.13 $\mu$ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic , 2011, IEEE Journal of Solid-State Circuits.

[26]  Myeong-Eun Hwang,et al.  Process-Tolerant Ultralow Voltage Digital Subthreshold Design , 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[27]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[28]  Anantha Chandrakasan,et al.  Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[29]  Yu Pu.  An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage , 2010 .