Joint Mismatch and Channel Compensation for High-Speed OFDM Receivers with Time-Interleaved ADCs

Analog-to-digital converters (ADCs) with high sampling rates and output resolution are required for the design of mostly digital transceivers in emerging multi-Gigabit communication systems. A promising approach is to use a time-interleaved (TI) architecture with slower sub-ADCs in parallel, but mismatch among the sub-ADCs, if left uncompensated, can cause error floors in receiver performance. Conventional mismatch compensation schemes typically have complexity (in terms of number of multiplications) that increases with the desired resolution at the output of the TI-ADC. In this paper, we investigate an alternative approach, in which mismatch and channel dispersion are compensated jointly, with the performance metric being overall link reliability rather than ADC performance. For an OFDM system, we characterize the structure of mismatch-induced interference, and demonstrate the efficacy of a frequency-domain interference suppression scheme whose complexity is independent of constellation size (which determines the desired resolution). Numerical results from computer simulation and from experiments on a hardware prototype show that the performance with the proposed joint mismatch and channel compensation technique is close to that without mismatch. While the proposed technique works with offline estimates of mismatch parameters, we provide an iterative, online method for joint estimation of mismatch and channel parameters which leverages the training overhead already available in communication signals.

[1]  Minyue Fu,et al.  Linear LMS Compensation for Timing Mismatch in Time-Interleaved ADCs , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Upamanyu Madhow,et al.  Multi-Gigabit communication: the ADC bottleneck1 , 2009, 2009 IEEE International Conference on Ultra-Wideband.

[3]  C.W. Bostian,et al.  Analog to Digital Converters , 2020, Embedded Systems Design using the MSP430FR2355 LaunchPad™.

[4]  Jared Tanner,et al.  Fast Reconstruction Methods for Bandlimited Functions from Periodic Nonuniform Sampling , 2006, SIAM J. Numer. Anal..

[5]  Fredrik Gustafsson,et al.  Analysis of mismatch effects in a randomly interleaved A/D converter system , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  A. Varzaghani,et al.  A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization , 2009, IEEE Journal of Solid-State Circuits.

[7]  Bernard C. Levy,et al.  Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Upamanyu Madhow.  Fundamentals of Digital Communication: References , 2008 .

[9]  Liesbet Van der Perre,et al.  A low complexity ML channel estimator for OFDM , 2001, ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240).

[10]  Håkan Johansson,et al.  Time-interleaved analog-to-digital converters: status and future directions , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[11]  Fredrik Gustafsson,et al.  Blind equalization of time errors in a time-interleaved ADC system , 2005, IEEE Transactions on Signal Processing.

[12]  Jean-François Naviner,et al.  Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Kenneth W. Martin,et al.  A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Patrick Satarzadeh,et al.  Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[15]  Boris Murmann,et al.  System embedded ADC calibration for OFDM receivers , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  A. J. Jerri.  The Shannon sampling theorem—Its various extensions and applications: A tutorial review , 1977, Proceedings of the IEEE.

[17]  Jingbo Wang,et al.  A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture , 2006, IEEE Journal of Solid-State Circuits.

[18]  Bernard C. Levy,et al.  Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[20]  Bram Nauta,et al.  A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[21]  Upamanyu Madhow,et al.  Multi-Gigabit Communication : the ADC Bottleneck , 2009 .

[22]  B.P. Ginsburg,et al.  Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[23]  U. Madhow,et al.  Comprehensive digital correction of mismatch errors for a 400-msamples/s 80-dB SFDR time-interleaved analog-to-digital converter , 2005, IEEE Transactions on Microwave Theory and Techniques.

[24]  Håkan Johansson,et al.  Reconstruction of nonuniformly sampled bandlimited signals by means of digital fractional delay filters , 2002, IEEE Trans. Signal Process..

[25]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification , 2008, 2008 IEEE Symposium on VLSI Circuits.

[26]  Upamanyu Madhow,et al.  Generalized Blind Mismatch Correction for Two-Channel Time-Interleaved A-to-D Converters , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

[27]  Yonina C. Eldar,et al.  Filterbank reconstruction of bandlimited signals from nonuniform and generalized samples , 2000, IEEE Trans. Signal Process..

[28]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[29]  Upamanyu Madhow,et al.  On the limits of communication with low-precision analog-to-digital conversion at the receiver , 2009, IEEE Transactions on Communications.

[30]  Ronan Farrell,et al.  Impact of Time-interleaved Analog-to-Digital ConverterMismatch on Digital Receivers , 2008 .

[31]  S. Adee,et al.  the data: 37 Years of Moore's Law , 2008, IEEE Spectrum.