Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

As semiconductor technology advances into the nanoscale era and more functional blocks are added into systems-on-chip, the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit-performance degradation comes from deterministic within-die variation from lithography imperfections and Cu-interconnect chemical-mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, we need a new analysis tool. Thus, we have proposed a methodology to involve layout-dependent within-die variations in static timing analysis. Our methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation

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