Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness.

[1]  B. Narasimham,et al.  Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[2]  Sinan Kaptanoglu,et al.  Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy , 2007, TRETS.

[3]  Habib Mehrez,et al.  A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs , 2013, Microelectron. Reliab..

[4]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Charles E. Stroud,et al.  BIST-based test and diagnosis of FPGA logic blocks , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Zied Marrakchi,et al.  Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[7]  C.W. Slayman,et al.  Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations , 2005, IEEE Transactions on Device and Materials Reliability.

[8]  Vaughn Betz,et al.  How Much Logic Should Go in an FPGA Logic Block? , 1998, IEEE Des. Test Comput..

[9]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[10]  Euiseok Hwang,et al.  Scrubbing with partial side information for radiation-tolerant memory , 2010, 2010 IEEE Globecom Workshops.

[11]  Zied Marrakchi,et al.  The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[12]  Lorena Anghel,et al.  BIST for logic and local interconnect resources in a novel mesh of cluster FPGA , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[13]  RoseJonathan,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[14]  Guy Lemieux,et al.  Using sparse crossbars within LUT , 2001, FPGA '01.

[15]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[16]  Mike Hutton,et al.  Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation , 2003, SLIP '03.

[17]  Zied Marrakchi,et al.  Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture , 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

[18]  Z. Marrakchi,et al.  Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter , 2006, 2006 Ph.D. Research in Microelectronics and Electronics.

[19]  Lirida A. B. Naviner,et al.  FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level , 2011, Microelectron. Reliab..

[20]  Russell Tessier,et al.  Interconnect testing in cluster-based FPGA architectures , 2000, Proceedings 37th Design Automation Conference.

[21]  Jonathan Rose,et al.  Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency , 1990 .

[22]  Vaughn Betz,et al.  Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.