A high performance IDDQ testable cache for scaled CMOS technologies

Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for a high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of gated-ground (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to the stacking effect of the transistor without significantly affecting performance. Simulation results for a 64 K cache show 20% average improvement in IDDQ sensitivity for TSMC 0.25 /spl mu/m technology, while the improvement is more than 1000% for the 70 nm predictive technology model.

[1]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[2]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[3]  T. Chen,et al.  Assessing SRAM test coverage for sub-micron CMOS technologies , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[4]  Víctor H. Champac,et al.  I/sub DDQ/ testing of opens in CMOS SRAMs , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[5]  K. Roy,et al.  DRG-cache: a data retention gated-ground cache for low power , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[6]  Victor Champac,et al.  6.1 IDDQ Testing of Opens in CMOS SRAMs , 1998 .

[7]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[8]  J.M. Soden.  I/sub DDQ/ testing for submicron CMOS IC technology qualification , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[9]  J. Segura,et al.  A detailed analysis of CMOS SRAM's with gate oxide short defects , 1997 .

[10]  M. Hashizume,et al.  CMOS SRAM functional test with quiescent write supply current , 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

[11]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[12]  D. M. H. Walker,et al.  Improvement of SRAM-based failure analysis using calibrated Iddq testing , 1996, Proceedings of 14th VLSI Test Symposium.

[13]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[14]  Bas Verhelst,et al.  Functional and I/sub DDQ/ testing on a static RAM , 1990, Proceedings. International Test Conference 1990.

[15]  Kaushik Roy,et al.  I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions , 2002, IEEE Design & Test of Computers.

[16]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.