The electrical, mechanical properties of through-silicon-via insulation layer for 3D ICs

This paper descibes variety of methods to examine the electrical and physical characteristics of the isolation layer deposited on TSV(Through-Si-Via). A sample was manufactured for the experiment with a diameter of 10μm and a depth of 50μm using Deep-RIE(Reactive Ion Etching). SiO2 thin-film was deposited on the TSV sample by two separate procedures: PECVD (Plasma Enhanced Chemical Vapor Deposition) and PETEOS (PE Tetra-Ethyl-Ortho-Silicate). The insulating layer of TSV is supposed to decrease inter-diffusion between materials that fill the wall and its interior, improve adhesion and prevent electrical leakage. Hence, physical deposition characteristics, such as the surface step coverage, deposition rate, and film's density were observed and analyzed in order to determine if the deposited layer met the above criteria. The results confirmed that the thin layer deposited by PETEOS deposition was superior to that formed by PECVD in every category considered. Moreover, in order to assess the electrical characteristics, the interior of via hole was filled with copper (Cu) using the damascene process to create a sample. I-V was measured using the Time Dependent Dielectric Breakdown (TDDB) method for the sample, The measurement values were used to check the voltage level where the leakage current appeared. These experiment results indicate that the failure rate of the insulating layer depends upon the film's thickness and the deposition process. This assertion provides clues for conjecturing the main causes of insulation destruction. In this study, we determined the best deposition process for insulating the interior of TSV and the optimal insulating layer thickness in relation to the usage voltage.

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