A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

[1]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[2]  R. Heald,et al.  Variability in sub-100nm SRAM designs , 2004, ICCAD 2004.

[3]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[4]  Koji Nii,et al.  Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  K. Ishibashi,et al.  A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..