Symbolic Parasitic Extractor for Circuit Simulation (SPECS)

This paper describes the design, development and implementation of the program SPECS. The purpose of SPECS is to automatically extract from a Rockwell microelectronic symbolic matrix description a netlist for circuit simulation. This program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective TRACE, i.e., traces only the circuit or network of interest.

[1]  Rathin Putatunda.  Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips , 1982, DAC 1982.

[2]  Yen-Son Huang,et al.  A Hierarchical Approach for Layout Versus Circuit Consistency Check , 1980, 17th Design Automation Conference.

[3]  W. H. Dierking,et al.  VLSI parasitic capacitance determination by flux tubes , 1982, IEEE Circuits & Systems Magazine.

[4]  Toshiro Akino,et al.  Circuit Simulation and Timing Verification based on MOS/LSI Mask Information , 1979, 16th Design Automation Conference.

[5]  Kenji Yoshida,et al.  An Integrated Mask Artwork Analysis System , 1980, 17th Design Automation Conference.

[6]  N. Shigyo,et al.  Coupling capacitances for two-dimensional wires , 1981, IEEE Electron Device Letters.

[7]  P. M. Hall,et al.  Resistance calculations for thin film patterns , 1968 .

[8]  Vishwani D. Agrawal.  Synchronous Path Analysis in MOS Circuit Simulator , 1982, DAC 1982.

[9]  Vishwani D. Agrawal.  Synchronous Path Analysis in MOS Circuit Simulator , 1982, 19th Design Automation Conference.

[10]  N. H. E. Weste.  Mulga — an interactive symbolic layout system for the design of integrated circuits , 1981, The Bell System Technical Journal.

[11]  Paul Losleben,et al.  Topological Analysis for VLSI Circuits , 1979, 16th Design Automation Conference.

[12]  T. Ozaki,et al.  PANAMAP-B: A Mask Verification System for Bipolar IC , 1981, 18th Design Automation Conference.