Post-Silicon Test Flow for Aging Prediction

Aging as a reliability parameter is often tested with elevated temperature or supply voltage (burn-in) environment, which is expensive and may damage product in the process. It has been found that circuit aging is primary due to signal stress conditions. And the aging effects will manifest on long critical paths for induced extra delays. In this paper, we proposed a test flow to predict timing-failure age caused by Negative-Bias Temperature Instability (NBTI). First, the flow measures critical path delays (which may variate due to process variation). Given the tested path delays, we sample a batch of delay profiles of cells on tested paths. Next, we simulate above delay profiles with known signal stress conditions (from functional simulation) to predict the failure age. In experimental results, comparing with reference golden sample (with known ages), we can obtain a very close prediction of failure ages (