Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip

System on chip (SoC) design requires efficient communication between heterogeneous resources to meet the high-speed transmission needs. Therefore one of the key factors for the success of ultra-deep submicron technologies will be the capability of integrating different resources like processor core, memory, an FPGA, a custom hardware block or any other semiconductor intellectual property (SIP) block into a single piece of silicon. Non-scalable global wire delays, global synchronization failure, loss of signal integrity issues are the main problems. To address these problems, various interconnect architectures are proposed. Butterfly fat tree (BFT) is one of those. To improve the performance of BFT we introduce extended-butterfly fat tree interconnection (EFTI). Routing algorithm is provided for EFTI and comparative analysis is performed through the simulation result.

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