Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip
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[1] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[2] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[3] Sujit Dey,et al. On-chip communication architecture for OC-768 network processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[4] Partha Pratim Pande,et al. Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[5] Ronald I. Greenberg,et al. An improved analytical model for wormhole routed networks with application to butterfly fat-trees , 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).
[6] William J. Dally,et al. The torus routing chip , 2005, Distributed Computing.
[7] Partha Pratim Pande,et al. High-throughput switch-based interconnect for future SoCs , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..
[8] Johnny Öberg,et al. Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.
[9] William J. Dally,et al. Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[10] Jari Nurmi,et al. Interconnect IP node for future system-on-chip designs , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.
[11] Martti Forsell,et al. A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.
[12] William J. Dally. Virtual-Channel Flow Control , 1992, IEEE Trans. Parallel Distributed Syst..
[13] Drew Wingard. MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[14] Partha Pratim Pande,et al. A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[15] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.