Timing-driven routing for symmetrical array-based FPGAs

In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, the traditional measure of routing delay on the basis of geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing rees, arising from the special properties of FPGA routing architectures. Based on the solutions to the routing-tree problem, we present a routing algorithm that is able to utilize various routing segments with global considerations to meet timing constraints. Experimental results show that our approach is very effective in reducing timing violations.

[1]  Jon Frankle,et al.  Iterative and adaptive slack allocation for performance-driven layout and FPGA routing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[2]  Malgorzata Marek-Sadowska.  Issues in Timing Driven Layout , 1993, Algorithmic Aspects of VLSI Layout.

[3]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[4]  Martin D. F. Wong,et al.  Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs , 1994, 31st Design Automation Conference.

[5]  Peter Suaris,et al.  A quadrisection-based combined place and route scheme for standard cells , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[7]  Samir Khuller,et al.  Balancing Minimum Spanning and Shortest Path Trees , 1993, SODA.

[8]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[9]  Allen C.-H. Wu,et al.  A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, 32nd Design Automation Conference.

[10]  Martin D. F. Wong,et al.  Switch bound allocation for maximizing routability in timing-driven routing of FPGA's , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Joseph L. Ganley,et al.  Performance-oriented placement and routing for field-programmable gate arrays , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[12]  Zvonko G. Vranesic,et al.  Modelling Routing Delays in SRAM-based FPGAs , 1993 .

[13]  Melvin A. Breuer,et al.  A class of min-cut placement algorithms , 1988, DAC '77.

[14]  Mikael Palczewski.  Plane parallel A* maze router and its application to FPGAs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[15]  R. Prim.  Shortest connection networks and some generalizations , 1957 .

[16]  Youn-Long Lin,et al.  TRACER-fpga: a router for RAM-based FPGA's , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Scott M. Brown.  Routing architectures and algorithms for field-programmable gate arrays , 1992 .

[18]  Yao-Wen Chang,et al.  Algorithms for an FPGA switch module routing problem with application to global routing , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Chak-Kuen Wong,et al.  Minimum Diameter Spanning Trees and Related Problems , 1991, SIAM J. Comput..

[20]  Yao-Wen Chang,et al.  A new global routing algorithm for FPGAs , 1994, ICCAD '94.

[21]  Guy Lemieux,et al.  On two-step routing for FPGAS , 1997, ISPD '97.

[22]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Gabriel Robins,et al.  New Performance-Driven FPGA Routing Algorithms , 1996, 32nd Design Automation Conference.

[24]  Snezana Lawrence.  October , 1855, The Hospital.

[25]  Allen C.-H. Wu Yuh-Sheng Lee.  A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, DAC 1995.

[26]  Baruch Awerbuch,et al.  Cost-sensitive analysis of communication protocols , 1990, PODC '90.

[27]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[28]  Yao-Wen Chang,et al.  Routing architectures and algorithms for field-programmable gate arrays , 1996 .

[29]  Kenneth Steiglitz,et al.  Combinatorial Optimization: Algorithms and Complexity , 1981 .

[30]  Jonathan Rose,et al.  A detailed router for field-programmable gate arrays , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[31]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.