POSFET touch sensing transducers: Interface electronics design methodology based on the transconductance-to-drain-current efficiency gm/ID

Abstract This paper deals with tactile sensing systems based on a piezoelectric polymer poly(vinylidene fluoride-trifluoroethylene) film on the gate area of a MOS (Metal Oxide Semiconductor) transistor: Piezoelectric Oxide Semiconductor Field Effect Transistor, POSFET. More specifically, we present the design and analysis of the interface electronic circuit between the touch sensor transducer and the signal conditioning circuit stage. The circuit configuration is based on a NMOS transistor in common-drain and floating gate bias configuration. Such configuration enhances and complements the transducer's response. However, the circuit interface design suffers of the very difficult analytical tractability. For this reason, a graphical methodology, intended to give a criterion for achieving the selection of the most appropriate bias resistance value has been developed. The methodology utilizes the Advanced Compact MOSFET (ACM) model and the gm characteristic as function of the NMOS transistor drain current ID. A design space map shows confidence regions where the specifications such as touch sensing device gain, current consumption and source resistance value are met. The design methodology enables to push the performance of the POSFET by selecting the most appropriate bias resistance value and it reduces time-consuming iterations which are normally required. As a proof of concept of the proposed methodology, measurements as well as a design example are presented.