PERFORMANCE ANALYSIS OF LOAD FLOW COMPUTATION USING FPGA 1

Full-AC load flow constitutes a core compu- tation in power system analysis. Current techniques for solving full-AC load flow rely on the iterative solution of the load flow equations using the Newton-Raphson method, and the bulk of this computation is devoted to solving a sparse-linear system needed for the update each iteration. In this paper, we evaluate the performance gain that is possible with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA). Using benchmark data, from four repre- sentative power systems, we compare the performance of a software solution using UMFPACK, a state-of-the-art sparse linear solver, running on a high-end PC with the proposed hardware solution. Performance of the hard- ware solution is obtained from a parameterized simulation of the hardware that allows a variety of architectural configurations and can take into account different FPGA technology. Our studies show that the proposed hardware solution can provide an order of magnitude performance gain using existing FPGA technology. however due to the irregular data flow and small granu- larity of the problem these methods do not scale well. In this paper we propose to use application-specific hardware to reduce the computation time for the solu- tion of the sparse linear systems arising in load flow computation. The use of special-purpose hardware reduces the overhead in computation, better utilizes floating-point hardware, and provides fine-grained parallelism. The use of Field Programmable Gate Ar- rays (FPGA) provides a convenient platform to design and implement such hardware. Other attempts have been made to utilize FPGAs to accelerate the computa- tion of sparse linear systems by using soft-core embed- ded processors on FPGAs (2). Our approach utilizes the FPGA resources differently. By building hardware that is specifically designed to solve the sparse matrices found in power system calculations, rather than utilizing general-purpose processors and parallel processing, we seek to improve the efficiency of the linear solver and hence reduce the computing time compared to tradi- tional platforms. In this paper, we describe the design of hardware for the direct solution of sparse linear systems. The hard- ware design takes advantage of properties of the matri- ces arising in power system computation obtained from a detailed analysis of actual power systems. A simula- tion study, using the benchmark systems is performed to compare the performance gain of the proposed hard- ware as compared to existing software solutions.