SC amplifier and SC integrator with an accurate gain of 2

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.

[1]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[2]  Bang-Sup Song,et al.  A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[3]  Sergio Pernici,et al.  Low-voltage double-sampled ΣΔ converters , 1997 .

[4]  G. Nicollini,et al.  Low-voltage double-sampled /spl Sigma//spl Delta/ converters , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  Gabor C. Temes,et al.  A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements , 1993 .

[6]  G. Temes.  Delta-sigma data converters , 1994 .

[7]  Hannu Tenhunen,et al.  A structure of cascading multi-bit modulators without dynamic element matching or digital correction , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[8]  I. Fujimori,et al.  A 90 dB SNR, 2.5 MHz output rate ADC using cascaded multibit /spl Delta//spl Sigma/ modulation at 8x oversampling ratio , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[9]  P. Quinn,et al.  Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m CMOS , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[10]  R. Castello,et al.  A ratio-independent algorithmic analog-to-digital conversion technique , 1984, IEEE Journal of Solid-State Circuits.

[11]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[12]  M. Segami,et al.  A 3.3 V, 12b, 50MSample/s A/D converter in 0.6 /spl mu/m CMOS with over 80 dB SFDR , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[13]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.