Energy Efficient Volatile Memory Circuits for the IoT Era

This chapter addresses the challenges involved in designing energy efficient embedded volatile Static Random Access Memory (SRAM) circuits for IoT era. It discusses memory design for wide voltage range operation using 6 Transistor (6T), 8T and 10T bitcells and novel circuit assist techniques. In addition, it discusses future memory designs using emerging nano-wire FET, Tunnel FET, III-V FET, and monolithic 3-D technologies.

[1]  Jiajing Wang,et al.  Impact of circuit assist methods on margin and performance in 6T SRAM , 2010 .

[2]  K. Roy,et al.  Technology Circuit Co-Design for Ultra Fast InSb Quantum Well Transistors , 2008, IEEE Transactions on Electron Devices.

[3]  Keith A. Bowman,et al.  PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[4]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[5]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[6]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Keith A. Bowman,et al.  Circuit techniques for dynamic variation tolerance , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[8]  Jaehoon Jang,et al.  Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[9]  Shunsuke Okumura,et al.  A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme , 2009, 2009 10th International Symposium on Quality Electronic Design.

[10]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[11]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Narayanan Vijaykrishnan,et al.  Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[13]  Keith A. Bowman,et al.  Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays , 2011, IEEE Journal of Solid-State Circuits.

[14]  Kaushik Roy,et al.  Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  J. Tschanz,et al.  Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance , 2009, 2009 Symposium on VLSI Circuits.

[16]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[17]  T. Karnik,et al.  Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[18]  H. Fujiwara,et al.  Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential — , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[19]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[20]  Masashi Horiguchi,et al.  Review and future prospects of low-voltage RAM circuits , 2003, IBM J. Res. Dev..