论文信息 - Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

The method of creating a parameterized spice model of an N-channel transistor with a gate of enclosed layout is considered. Formulas and examples of engineering calculations for use of models in the computer-aided Design environment of Cadence Vitruoso are presented. Calculations are made for the CMOS technology with 180 nm design rules of the UMC.

E. V. Atkin | S M Vinogradov | P. Ivanov

[1] Federico Faccio,et al. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects , 1999 .