Quasi-SOI MOSFETs—A Promising Bulk Device Candidate for Extremely Scaled Era

Results from a novel quasi-SOI CMOS architecture fabricated on bulk SI are reported for the first time, demonstrating its viability as an alternative device for the nanometer regime. All of the processing is basically compatible with the conventional CMOS technology. The short-channel effects and the drain-induced barrier-lowering effects can be effectively suppressed by the "L-type" insulator surrounding the source/drain regions. In addition, quasi-SOI MOSFETs can be more tolerant of process- induced variation for the deep nanometer regime. The quasi-SOI MOSFET can be considered as one of the promising candidates for highly scaled devices.

[2]  Jeffrey Bokor,et al.  Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.

[3]  H.-S.P. Wong,et al.  An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs , 2002, IEEE Electron Device Letters.

[4]  Chenming Hu,et al.  Self-heating characterization for SOI MOSFET based on AC output conductance , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[5]  Ru Huang,et al.  A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET , 2005 .

[6]  V. Narayanan,et al.  Device design considerations for ultra-thin SOI MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[7]  T. Numata,et al.  Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[8]  T. Numata,et al.  Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm , 2002, Digest. International Electron Devices Meeting,.

[9]  S. Takagi,et al.  Influences of buried-oxide interface on inversion-layer mobility in ultra-thin SOI MOSFETs , 2002 .

[10]  Stephane Monfray,et al.  Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices , 2001 .

[11]  R. Koh Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET , 1999 .