Effect of Raised Buried Oxide on Characteristics of Tunnel Field Effect Transistor

[1]  S. K. Sinha,et al.  Ge-Source Based L-Shaped Tunnel Field Effect Transistor for Low Power Switching Application , 2021, Silicon.

[2]  S. K. Sinha,et al.  Performance analysis of heterojunction tunnel FET device with variable Temperature , 2021, Applied Physics A.

[3]  C. Pandey,et al.  A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET , 2021, Microelectronics Reliability.

[4]  C. Pandey,et al.  Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap , 2021, Silicon.

[5]  Shradhya Singh,et al.  Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance , 2020 .

[6]  S. K. Sinha,et al.  Improvement of Electrical Characteristics of SiGe Source Based Tunnel FET Device , 2020, Silicon.

[7]  Yiming Li,et al.  New Proficient Ferroelectric Nanosheet Line Tunneling FETs with Strained SiGe through Scaled n-epitaxial Layer , 2020, 2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO).

[8]  Balraj Singh,et al.  Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance , 2020, IEEE Transactions on Electron Devices.

[9]  S. K. Sinha,et al.  Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs , 2019, Superlattices and Microstructures.

[10]  F. Djeffal,et al.  A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs , 2019, Silicon.

[11]  Ru Huang,et al.  A Novel Negative Capacitance Tunnel FET With Improved Subthreshold Swing and Nearly Non-Hysteresis Through Hybrid Modulation , 2019, IEEE Electron Device Letters.

[12]  B. Bhowmick,et al.  TFET on Selective Buried Oxide (SELBOX) Substrate with Improved ION/IOFF Ratio and Reduced Ambipolar Current , 2019, Silicon.

[13]  Bhagwan Ram Raad,et al.  A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics , 2017, IEEE Transactions on Electron Devices.

[14]  David Cavalheiro,et al.  Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Satyabrata Jit,et al.  A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure , 2016, IEEE Transactions on Electron Devices.

[16]  Amit Sharma,et al.  Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET , 2015, 2015 19th International Symposium on VLSI Design and Test.

[17]  Narayanan Vijaykrishnan,et al.  Tunnel FET technology: A reliability perspective , 2014, Microelectron. Reliab..

[18]  Hasan Al-Nashash,et al.  Thermal model of MOSFET with SELBOX structure , 2013 .

[19]  Takashi Matsukawa,et al.  Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations , 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[20]  A. Ionescu,et al.  TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model , 2012 .

[21]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[22]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[23]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[24]  D. Antoniadis,et al.  Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks , 2007 .

[25]  C. Hu,et al.  Germanium-source tunnel field effect transistors with record high ION/IOFF , 2006, 2009 Symposium on VLSI Technology.

[26]  G. Amaratunga,et al.  Silicon surface tunnel transistor , 1995 .

[27]  S. K. Sinha,et al.  Investigation of DC performance of Ge-source pocket silicon-on-insulator tunnel field effect transistor in nano regime , 2021 .

[28]  David Cavalheiro,et al.  TFET-Based Power Management Circuit for RF Energy Harvesting , 2017, IEEE Journal of the Electron Devices Society.

[29]  Vinod Kumar Khanna,et al.  Short-Channel Effects in MOSFETs , 2016 .

[30]  K. Boucart,et al.  Double-Gate Tunnel FET With High-κ Gate Dielectric , 2008 .

[31]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[32]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .