Design of flash memory arrays with SOI cells utilizing the back-channel based erase method

This paper demonstrates one way of designing a flash memory array which incorporates cells produced in Silicon-On-Insulator (SOl) technology. General principles of SOl flash memory cell operation are presented. SOl memory cells used in the design utilize a standard way to write information and a novel method to erase it. Performance analysis of the suggested design is carried out for a simple memory array. 16x16 memory chip layout is presented as an example.