Post-silicon timing characterization by compressed sensing
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[1] E.J. Candes. Compressive Sampling , 2022 .
[2] Pei-Ying Hsieh,et al. Exploring linear structures of critical path delay faults to reduce test efforts , 2006, ICCAD.
[3] David L Donoho,et al. Compressed sensing , 2006, IEEE Transactions on Information Theory.
[4] Sachin S. Sapatnekar,et al. Statistical timing analysis under spatial correlations , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] D. Sylvester,et al. A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[6] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[7] Keith A. Bowman,et al. Comparative Analysis of Conventional and Statistical Design Techniques , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[8] Jinjun Xiong,et al. Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] David Blaauw,et al. Statistical timing analysis for intra-die process variations with spatial correlations , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[10] David Blaauw,et al. Statistical Analysis and Optimization for VLSI: Timing and Power , 2005, Series on Integrated Circuits and Systems.
[11] Weiping Shi,et al. Longest-path selection for delay test under process variation , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] John J. Shedletsky,et al. An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.
[13] Tom W. Chen,et al. Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] Janak H. Patel,et al. Finding a small set of longest testable paths that cover every gate , 2002, Proceedings. International Test Conference.
[15] Sachin S. Sapatnekar,et al. Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[16] J. Plusquellic,et al. A test structure for characterizing local device mismatches , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
[17] Andrzej J. Strojwas,et al. Correlation-aware statistical timing analysis with non-Gaussian delay distributions , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[18] Frank Liu,et al. A General Framework for Spatial Correlation Modeling in VLSI Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[19] Janak H. Patel,et al. Bounding circuit delay by testing a very small subset of paths , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[20] B. Cline,et al. Analysis and modeling of CD variation for statistical static timing , 2006, ICCAD '06.
[21] Yu Cao,et al. Mapping statistical process variations toward circuit performance variability: an analytical modeling approach , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[22] Sani R. Nassif,et al. An accurate sparse matrix based framework for statistical static timing analysis , 2006, ICCAD.
[23] Zhuo Feng,et al. Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[24] Jinjun Xiong,et al. Variation-aware performance verification using at-speed structural test and statistical timing , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.