DVGen: IncreasingCoverage by Automatically Combining TestSpecifications

DVGenisanovel microprocessor test generator that allows theverification engineer tofocus onlyoncapturing test intent viaminimally constrained test specifications. DVGencom- bines testspecifications togenerate tests thatpreserve theintent ofeachspecification while causing theconcurrent occurrence of interesting events fromeachspecification. DVGenisveryeffective atuncovering multi-dimensional cornercasebugs, whichhave historically beenthebaneofcomplex designs.