A layout-based approach for Multiple Event Transient analysis

With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout-based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is proposed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER.

[1]  Mehdi Baradaran Tahoori,et al.  Chip-level modeling and analysis of electrical masking of soft errors , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[2]  P. Reviriego,et al.  Reliability Analysis of Memories Suffering Multiple Bit Upsets , 2007, IEEE Transactions on Device and Materials Reliability.

[3]  J. Furuta,et al.  An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets , 2011, IEEE Transactions on Nuclear Science.

[4]  Régis Leveugle,et al.  Statistical fault injection: Quantified error and confidence , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Pedro Reviriego,et al.  Study of the effects of MBUs on the reliability of a 150 nm SRAM device , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[6]  Cecilia Metra,et al.  Error correcting code analysis for cache memory high reliability and performance , 2011, 2011 Design, Automation & Test in Europe.

[7]  Narayanan Vijaykrishnan,et al.  SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[8]  Liang Chen,et al.  CLASS: Combined logic and architectural soft error sensitivity analysis , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[9]  Diana Marculescu,et al.  Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  B. L. Bhuva,et al.  Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process , 2011, IEEE Transactions on Nuclear Science.

[11]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[12]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[13]  Rong Luo,et al.  A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Mehdi Baradaran Tahoori,et al.  Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs) , 2011, 2011 Design, Automation & Test in Europe.

[15]  Mahdi Fazeli,et al.  A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design , 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

[16]  Cecilia Metra,et al.  Multiple transient faults in logic: an issue for next generation ICs? , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[17]  Mehdi Baradaran Tahoori,et al.  Efficient algorithms to accurately compute derating factors of digital circuits , 2012, Microelectron. Reliab..

[18]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[19]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[20]  P. Roche,et al.  Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs , 2008, IEEE Transactions on Nuclear Science.

[21]  H. Puchner,et al.  Investigation of multi-bit upsets in a 150 nm technology SRAM device , 2005, IEEE Transactions on Nuclear Science.

[22]  Zhu Ming,et al.  Reliability of Memories Protected by Multibit Error Correction Codes Against MBUs , 2011, IEEE Transactions on Nuclear Science.

[23]  Diana Marculescu,et al.  Modeling and Optimization for Soft-Error Reliability of Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Seyed Ghassem Miremadi,et al.  SCFIT: A FPGA-based fault injection technique for SEU fault model , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[26]  Lorena Anghel,et al.  Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[27]  Masanori Hashimoto,et al.  Neutron induced single event multiple transients with voltage scaling and body biasing , 2011, 2011 International Reliability Physics Symposium.

[28]  Alan Wood,et al.  The impact of new technology on soft error rates , 2011, 2011 International Reliability Physics Symposium.

[29]  Naresh R. Shanbhag,et al.  Sequential Element Design With Built-In Soft Error Resilience , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  N. Seifert,et al.  Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node , 2009, 2009 IEEE International Reliability Physics Symposium.