Multi-Gate MOSFET Compact Model BSIM-MG

As the scaling of conventional planar CMOS is reaching its limits, multiple-gate CMOS structures will likely take up the baton. To facilitate circuit simulation in such advanced technologies, we have developed BSIM-MG: a versatile compact model for multi-gate MOSFETs. In this chapter separate formulations for common multi-gate and independent multi-gate MOSFETs are presented. The core I-V and C-V models are derived and agree well with TCAD simulations without using fitting parameters, reflecting the predictivity and scalability of the model. Physical effects such as volume inversion, short channel effects and quantum mechanical effects are included in the model. We verify BSIM-MG against triple-gate SOI FinFET experimental data. The model fits data very well across a wide range of biases, gate lengths and temperatures. It is also computationally efficient and suitable for simulating large circuits. Finally, several multi-gate circuit simulation examples are presented to demonstrate the use of the model.

[1]  C. Hu,et al.  BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[2]  Mohan Vamsi Dunga,et al.  Nanoscale CMOS modeling , 2008 .

[3]  G. Dewey,et al.  Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[4]  Kok Wai Wong,et al.  Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation , 2002, Digest. International Electron Devices Meeting,.

[5]  G. Pei,et al.  A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description , 2003 .

[6]  Chenming Hu,et al.  Performance-Aware Corner Model for Design for Manufacturing , 2009, IEEE Transactions on Electron Devices.

[7]  M. Silberstein,et al.  A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.

[8]  Yukihito Kondo,et al.  Suspended Gold Nanowires: Ballistic Transport of Electrons , 2001 .

[9]  C. Hu,et al.  High-field transport of inversion-layer electrons and holes including velocity overshoot , 1997 .

[10]  Yang-Kyu Choi,et al.  35 nm CMOS FinFETs , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[11]  D. Fried,et al.  High-performance p-type independent-gate FinFETs , 2004, IEEE Electron Device Letters.

[12]  Bing J. Sheu,et al.  BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .

[13]  Zheng Guo,et al.  FinFET-based SRAM design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[14]  C. Hu,et al.  Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs , 2004 .

[15]  J. Brews A charge-sheet model of the MOSFET , 1978 .

[16]  V. Trivedi,et al.  Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs , 2005, IEEE Electron Device Letters.

[17]  G.D.J. Smit,et al.  Symmetric linearization method for double-gate and surrounding-gate MOSFET models , 2009 .

[19]  A. Asenov Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[20]  T. Sugii,et al.  Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's , 1995 .

[21]  C. Hu,et al.  Threshold voltage model for deep-submicrometer MOSFETs , 1993 .

[22]  Chenming Calvin Hu,et al.  Modern Semiconductor Devices for Integrated Circuits , 2009 .

[23]  Kinam Kim,et al.  A high performance 16M DRAM on a thin film SOI , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[24]  Chenming Hu,et al.  Self-heating characterization for SOI MOSFET based on AC output conductance , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[25]  Samel K. H. Fung,et al.  BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs , 2000, Proceedings of the IEEE Custom Integrated Circuits Conference.

[26]  C. Hu,et al.  BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design , 2007, 2007 IEEE Symposium on VLSI Technology.

[27]  Dimitri A. Antoniadis,et al.  Back-gated CMOS on SOIAS for dynamic threshold voltage control , 1997 .

[28]  Christian Enz,et al.  A Design Oriented Charge-based Current Model for Symmetric DG MOSFET and its Correlation with the EKV Formalism , 2005 .

[29]  Mark S. Lundstrom Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[30]  R. Rooyackers,et al.  A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM , 2007, 2007 IEEE Symposium on VLSI Technology.

[31]  Ali M. Niknejad,et al.  Global parameter extraction for a multi-gate MOSFETs compact model , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

[32]  Chung-Hsun Lin,et al.  A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation , 2007, 2007 IEEE International Electron Devices Meeting.

[33]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[34]  G. O. Workman,et al.  A process/physics-based compact model for nonclassical CMOS device and circuit design , 2004 .

[35]  Yuhua Cheng,et al.  MOSFET Modeling and Bsim3 User's Guide , 1999 .

[36]  Jean-Pierre Colinge,et al.  FinFETs and Other Multi-Gate Transistors , 2007 .

[37]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[38]  C. Hu,et al.  A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors , 1990 .

[39]  Ali M. Niknejad,et al.  Design of FinFET SRAM Cells Using a Statistical Compact Model , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[40]  Ali M. Niknejad,et al.  BSIM-CMG: A Compact Model for Multi-Gate Transistors , 2008 .

[41]  M. Ieong,et al.  Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[42]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[43]  Mansun Chan,et al.  Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's , 1995 .

[44]  Y. Taur An analytical solution to a double-gate MOSFET with undoped body , 2000 .

[45]  Soo-Young Oh,et al.  Transient analysis of MOS transistors , 1980 .

[46]  Yuan Taur,et al.  An analytic potential model for symmetric and asymmetric DG MOSFETs , 2006 .

[47]  Chenming Hu,et al.  Modeling Advanced FET Technology in a Compact Model , 2006, IEEE Transactions on Electron Devices.

[48]  Chenming Hu,et al.  Gate-induced band-to-band tunneling leakage current in LDD MOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[49]  Y. Taur,et al.  A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[50]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .

[51]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[52]  Chung-Hsun Lin,et al.  Compact Modeling of Nanoscale CMOS , 2007 .

[53]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .