Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application

This paper presents a reconfigurable SAD Tree (RSADT) architecture based on adaptive sub-sampling algorithm for HDTV application. Firstly, to obtain the the feature of HDTV picture, pixel difference analysis is applied on each macroblock (MB). Three hardware friendly sub-sampling patterns are selected adaptively to release complexity of homogeneous MB and keep video quality for texture MB. Secondly, since two pipeline stages are inserted, the whole clock speed of RSADT structure is enhanced. Thirdly, to solve data reuse and hardware utilization problem of adaptive algorithm, the RSADT structure adopts pixel data organization in both memory and architecture level, which leads to full data reuse and hardware utilization. Additionally, a cross reuse structure is proposed to efficiently generate 16 pixel scaled configurable SAD (sum of absolute difference). Experimental results show that, our RSADT architecture can averagely save 61.71% processing cycles for integer motion estimation engine and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency of our design is 208MHz under TSMC 0.18µm technology in worst work conditions(1.62V, 125°C). Furthermore, the proposed algorithm and reconfigurable structure are favorable to power aware real-time encoding system.

[1]  Liang-Gee Chen,et al.  Analysis and architecture design of variable block-size motion estimation for H.264/AVC , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Yang Song,et al.  A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC , 2006, IEICE Trans. Electron..

[3]  Yang Song,et al.  HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis , 2009, IEEE Journal of Solid-State Circuits.

[4]  John V. McCanny,et al.  A VLSI architecture for variable block size video motion estimation , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Liang-Gee Chen,et al.  An H.264/AVC scalable extension and high profile HDTV 1080p encoder chip , 2008, 2008 IEEE Symposium on VLSI Circuits.

[6]  Minho Kim,et al.  A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264 , 2005, ASP-DAC '05.

[7]  S. Mochizuki,et al.  A low power and high picture quality H.264/MPEG-4 video codec IP for HD mobile applications , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[8]  Jiun-In Guo,et al.  A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  Liang-Gee Chen,et al.  Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[10]  Liang-Gee Chen,et al.  2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications , 2007, 2007 IEEE Symposium on VLSI Circuits.

[11]  Yang Song,et al.  Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[12]  Liang-Gee Chen,et al.  A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  Liang-Gee Chen,et al.  Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[14]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..