Shaping a VLSI wire to minimize Elmore delay

Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.

[1]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[2]  Jaijeet Roychowdhury Avoiding dispersion in distributed RLC lines by shaping , 1995, Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95).

[3]  John Philip Fishburn,et al.  Shaping a distributed-rc line to minimize elmore delay , 1995 .

[4]  Andrew B. Kahng,et al.  Fidelity and near-optimality of Elmore-based routing constructions , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[5]  Hai Zhou,et al.  Optimal non-uniform wire-sizing under the Elmore delay model , 1996, Proceedings of International Conference on Computer Aided Design.

[6]  Jason Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, ICCAD '93.

[7]  庄司 正一,et al.  CMOS digital circuit technology , 1988 .

[8]  Kurt Keutzer,et al.  Algorithms and Techniques for VLSI Layout and Synthesis , 1988 .

[9]  Daniel W. Dobberpuhl,et al.  The design and analysis of VLSI circuits , 1985 .

[10]  Charlie Chung-Ping Chen,et al.  Optimal wire-sizing formula under the Elmore delay model , 1996, DAC '96.

[11]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[12]  R. Courant,et al.  Introduction to Calculus and Analysis , 1991 .

[13]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[14]  Burton M. Leary,et al.  A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[15]  Leonhard Euler Methodus inveniendi lineas curvas maximi minimive proprietate gaudentes, sive solutio problematis isoperimetrici latissimo sensu accepti , 2013, 1307.7187.

[16]  Charlie Chung-Ping Chen,et al.  Optimal wire-sizing function with fringing capacitance consideration , 1997, DAC.

[17]  Jirí Vlach,et al.  Group delay as an estimate of delay in logic , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..