论文信息 - Using Formal Veriication Techniques to Reduce Simulation and Test Eeort

Using Formal Veriication Techniques to Reduce Simulation and Test Eeort

This paper describes an experiment in using formal methods in an industrial context. The goal is to use formal veriication techniques in order to alleviate the simulation and test activities. The application is a ight control computer of the Airbus A340.

P. Michel | V. Wiels

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