论文信息 - Execution Efficiency of the Microthreaded Pipeline

Execution Efficiency of the Microthreaded Pipeline

When analyzing execution efficiency of the microthreaded pipeline, we are interested in two key things: 1. The number of stall clock cycles in the processing pipeline. 2. The latency tolerance for blocking and non-blocking long-latency operations.

Roman Bartosiński | Martin Daněk | Leoš Kafka | Lukáš Kohout | Jaroslav Sýkora

[1] Kunle Olukotun,et al. Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[2] Chris R. Jesshope. muTC - An Intermediate Language for Programming Chip Multiprocessors , 2006, Asia-Pacific Computer Systems Architecture Conference.

[3] Kevin D. Kissell,et al. MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing , 2008, HiPEAC.

[4] William E. Weihl,et al. Register relocation: flexible contexts for multithreading , 1993, ISCA '93.

[5] Chris R. Jesshope,et al. Micro-threading: a new approach to future RISC , 2000, Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512).

[6] David E. Culler,et al. Analysis of multithreaded architectures for parallel computing , 1990, SPAA '90.

[7] Theo Ungerer,et al. A survey of processors with explicit multithreading , 2003, CSUR.

[8] Jeffrey Su,et al. A dual-core 64-bit ultraSPARC microprocessor for dense server applications , 2004, IEEE Journal of Solid-State Circuits.

[9] Arvind,et al. Executing a Program on the MIT Tagged-Token Dataflow Architecture , 1990, IEEE Trans. Computers.

[10] Chris R. Jesshope. Scalable Instruction-Level Parallelism , 2004, SAMOS.

[11] Avi Mendelson,et al. Many-Core vs. Many-Thread Machines: Stay Away From the Valley , 2009, IEEE Computer Architecture Letters.