Synthesis of power efficient systems-on-silicon

We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in three steps: minimization of instruction cache misses, placement of frequently executed sequential basic blocks of code in consecutive Gray code addressed memory locations, and processor and cache application-driven selection for low power. In order to bridge the gap between the profiling and modeling tools from the two traditionally disjoint synthesis domains (architecture and CAD), we developed a new synthesis and evaluation platform. The platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern industrial-strength multimedia and communication applications.

[1]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[2]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[3]  W. W. Hwu,et al.  Achieving high instruction cache performance with an optimizing compiler , 1989, ISCA '89.

[4]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[5]  Michael J. Flynn,et al.  Computer Architecture: Pipelined and Parallel Processor Design , 1995 .

[6]  Miodrag Potkonjak,et al.  Application-driven synthesis of core-based systems , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[7]  Brian N. Bershad,et al.  Avoiding conflict misses dynamically in large direct-mapped caches , 1994, ASPLOS VI.

[8]  K. Yelick,et al.  The Energy Efficiency Of Iram Architectures , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[9]  Jan M. Rabaey,et al.  Low-power architectural synthesis and the impact of exploiting locality , 1996, J. VLSI Signal Process..

[10]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[11]  Frank Vahid,et al.  A system-design methodology: executable-specification refinement , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[12]  George Papageorgiou,et al.  The Complexity of Cubical Graphs , 1985, Inf. Control..

[13]  Wayne Wolf,et al.  Hardware-software co-design of embedded systems , 1994, Proc. IEEE.

[14]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[15]  Masato Nagamatsu,et al.  A 150 MIPS/W CMOS RISC processor for PDA applications , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[16]  Nikil D. Dutt,et al.  Memory organization for improved data cache performance in embedded processors , 1996, Proceedings of 9th International Symposium on Systems Synthesis.

[17]  Miodrag Potkonjak,et al.  Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques , 1995, ICCAD.

[18]  David Keppel,et al.  Shade: a fast instruction-set simulator for execution profiling , 1994, SIGMETRICS.

[19]  Thomas D. Burd,et al.  Processor design for portable systems , 1996, J. VLSI Signal Process..

[20]  Josep Torrellas,et al.  Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses , 1996, ISCA.

[21]  Mark D. Hill,et al.  A case for direct-mapped caches , 1988, Computer.

[22]  Paul D. Franzon,et al.  Energy consumption modeling and optimization for SRAM's , 1995, IEEE J. Solid State Circuits.

[23]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[24]  Alvin M. Despain,et al.  Cache design trade-offs for power and performance optimization: a case study , 1995, ISLPED '95.

[25]  T. Wada,et al.  An analytical access time model for on-chip cache memories , 1992 .

[26]  T. Izawa,et al.  A 500 MHz 288 kb CMOS SRAM macro for on-chip cache , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[27]  De-Sheng Chen,et al.  Cube-embedding based state encoding for low power design , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[28]  U. Ko,et al.  Characterization and design of a low-power, high-performance cache architecture , 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.