Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of stacked chip type 3-D SiP with vertically interconnected TSV are reported. The process includes; 55 mum-diameter via holes by reactive ion etching (RIE), SiO2 dielectric layer by thermal oxidation, Ta and Cu seed layers by ionized metal plasma (IMP), Cu via filling by electroplating, Cu/Sn bump for multi-chip stacking and finally chip-to-PCB bonding with Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP with 10 stacked chips was successfully fabricated. High frequency electrical model of the TSV was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. And then, contact resistances of Cu via and bump joint were discussed.

[1]  R.W. Brodersen,et al.  A portable multimedia terminal , 1992, IEEE Communications Magazine.

[2]  H. Baltes,et al.  Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers , 1994, Proceedings IEEE Micro Electro Mechanical Systems An Investigation of Micro Structures, Sensors, Actuators, Machines and Robotic Systems.

[3]  Robert E. Terrill.  Aladdin: Packaging lessons learned , 1995 .

[4]  M. Koyanagi,et al.  Three-Diensional Integration Technology Based on Wafer Bonding Technique Using Micro-Bumps , 1995 .

[5]  W. Pamler,et al.  Three dimensional metallization for vertically integrated circuits , 1997, European Workshop Materials for Advanced Metallization,.

[6]  Mitsumasa Koyanagi,et al.  Future system-on-silicon LSI chips , 1998, IEEE Micro.

[7]  Jürgen Wilde,et al.  3D Si-on-Si stack package , 1999 .

[9]  M. Tomisaka,et al.  Development of advanced 3D chip stacking technology with ultra-fine interconnection , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[10]  Manabu Bonkohara,et al.  Current Status of Research and Development for Three-Dimensional Chip Stack Technology , 2001 .

[11]  Yoshihiro Tomita,et al.  Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[12]  Through wafer via technology for 3-D packaging , 2005, 2005 6th International Conference on Electronic Packaging Technology.

[13]  New Chip-on-glass and Flip-chip Processes Using Interlocking Bump Structure Fabricated by Electrodeposition , 2006 .