효율적인 스케쥴링을 통한 MPEG4 디코더용 고성능 인트라 예측 및 스캔 회로 설계

This paper describes the architecture and design of high-performance intra prediction and scan circuit for MPEG4 decoder. We improved the circuit performance based on pipelining and scheduling. Inverse scan circuit uses 2-stage pipeline with two 64×12 buffers. We partitioned the intra prediction circuit into two modules for efficient scheduling. Our circuit consists of 31,614 gates and operates at the maximum operating frequency of 174㎒ with 130㎚ standard cells.