on Network Processors: the TILEPro64 Experience
暂无分享，去创建一个
[1] Andreas C. Döring,et al. A Comparison of Parallel Programming Models of Network Processors , 2004, ARCS Workshops.
[2] Philippas Tsigas,et al. Cache-Aware Lock-Free Queues for Multiple Producers/Consumers and Weak Memory Consistency , 2010, OPODIS.
[3] Henry Hoffmann,et al. On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.
[4] Marco Danelutto,et al. Parallel Patterns for General Purpose Many-Core , 2013, 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.
[5] Patrick P. C. Lee,et al. A lock-free, cache-efficient shared ring buffer for multi-core architectures , 2009, ANCS '09.
[6] Sarita V. Adve,et al. Shared Memory Consistency Models: A Tutorial , 1996, Computer.
[7] John Giacomoni,et al. FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue , 2008, PPoPP.
[8] Peter Kilpatrick,et al. An Efficient Unbounded Lock-Free Queue for Multi-core Systems , 2012, Euro-Par.