A novel peripheral circuit for RRAM-based LUT

Resistive random access memory (RRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design for its high density and non-volatility. RRAM cells are fabricated at backend CMOS process and have negligible area cost. However, the complex peripheral circuit design to satisfy performance and accuracy requirements becomes a major issue. In this work, we propose a novel peripheral circuit for RRAM-based LUT. A new decoding scheme that supports dynamic programming is introduced. Furthermore, the expanded RRAM crossbar array together with the latch comparator based sense amplifier can dramatically reduce design complexity, decrease area cost, and improve tolerance on process variations. Compared to a 6-input SRAM-based LUT, the proposed RRAM-based one cuts off 60.4% of layout area. The maximal operating frequency reaches 1GHz at 10mV input difference. Simulations also show that the proposed LUT functions properly even RRAM resistances deviates 20% from the design value.

[1]  P. Chow,et al.  The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Wei Zhang,et al.  3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[3]  I. Baek,et al.  Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  C. Hu,et al.  9nm half-pitch functional resistive memory cell with <1µA programming current using thermally oxidized sub-stoichiometric WOx film , 2010, 2010 International Electron Devices Meeting.

[5]  Swarup Bhunia,et al.  Computing with nanoscale memory: Model and architecture , 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

[6]  Byung Joon Choi,et al.  Purely Electronic Switching with High Uniformity, Resistance Tunability, and Good Retention in Pt‐Dispersed SiO2 Thin Films for ReRAM , 2011, Advanced materials.

[7]  Matthew D. Pickett,et al.  CMOS interface circuits for reading and writing memristor crossbar array , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[8]  Hao Yan,et al.  Programmable nanowire circuits for nanoprocessors , 2011, Nature.

[9]  Horst Zimmermann,et al.  A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  R. Dittmann,et al.  Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges , 2009, Advanced materials.

[12]  John Paul Strachan,et al.  The switching location of a bipolar memristor: chemical, thermal and structural mapping , 2011, Nanotechnology.

[13]  FPGA Architecture White Paper , 2006 .