This paper considers the continuous distribution HMM and discusses speed improvement by parallel processing and VLSI design, aiming at the realization of a high-speed speech recognition LSI. The continuous distribution HMM has high recognition performance. But a large amount of computation is required for the calculation of the output probability, and speed improvement is highly desirable. Regarding speed improvement of the output probability calculation, this paper proposes blockwise parallel processing and an architecture for performance. The minimum optimal bit width is investigated for recognition by fixed-point operations. Based on the proposed architecture, VLSI design for an HMM is performed and the result is evaluated. It is shown that the proposed architecture has sufficient power to construct a recognition system that can respond in real time, requiring 3 ms for the recognition processing of 100 words. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(5): 12–23, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10099
[1]
Hui Cheng,et al.
Vector pipelining, chaining, and speed on the IBM 3090 and Cray X-MP
,
1989,
Computer.
[2]
Satoshi Takahashi,et al.
On the use of scalar quantization for fast HMM computation
,
1995,
1995 International Conference on Acoustics, Speech, and Signal Processing.
[3]
Lawrence R. Rabiner,et al.
A tutorial on hidden Markov models and selected applications in speech recognition
,
1989,
Proc. IEEE.
[4]
Enrico Bocchieri,et al.
Vector quantization for the efficient computation of continuous density likelihoods
,
1993,
1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[5]
Peter Beyerlein,et al.
Fast log-likelihood computation for mixture densities in a high-dimensional feature space
,
1994,
ICSLP.
[6]
Vassilios Digalakis,et al.
Efficient speech recognition using subvector quantization and discrete-mixture HMMS
,
2000,
Comput. Speech Lang..