Design of low-power analog circuits for analog decoding and wireless sensors nodes

The first part of this work concerns analog decoding. It presents the design of the I/O interface for a fully analog iterative decoder for a serially concatenated convolutional code and of a fully analog Trellis Coded Modulation (TCM) decoder for error correction in multi-level (ML) flash memories. The iterative decoder represents a significant step ahead in the evolution of analog decoders due to its reconfigurability in both block length and code rate. Moreover, with an efficiency of 2.1nJ/bit, it outperforms digital decoders with the same block length of a factor up to 50. The potential performance and limitations of the analog approach for a TCM decoder have been investigated considering a 4-state and an 8-state decoder, both developed in a 0.18um standard CMOS process. In the second part of the thesis, the design of a low-power transceiver chipset for ultra wideband impulse radio (UWB-IR) is presented, with particular emphasis on the transmitter design. In particular, the transmitter uses a novel combined mixer and power amplifier to generate a Gaussian pulse with 1.25GHz bandwith and center frequency of 7.875GHz. The combined MRX-PA includes a monolithic transformer to reach a maximum output voltage swing of 3.2Vpp, necessary to ensure the required link distance of 10 meters. The transformer has been designed in order to maximize the power efficiency and at the same time to realize a fourth-order ladder filter, so as to reduce the transmitter out-of band emissions. The efficiency of this design has been compared with state-of-the-art UWB-IR transmitters, showing how the proposed solution leads to an improvement in the transmitter efficiency of a factor of almost 10.

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