Aging model challenges in deeply scaled tri-gate technologies
暂无分享,去创建一个
S. Mudanai | S. Ramey | C. Prasad | I. Meric | J. Hicks | Y. Lu | S. Novak | J. Hicks | C. Prasad | S. Ramey | I. Meric | S. Mudanai | S. Novak | Y. Lu
[1] Kaustav Banerjee,et al. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] C. Auth,et al. Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures , 2014, 2014 IEEE International Reliability Physics Symposium.
[3] S. John,et al. NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.
[4] Naoto Horiguchi,et al. Origins and implications of increased channel hot carrier variability in nFinFETs , 2015, 2015 IEEE International Reliability Physics Symposium.
[5] N. Mielke,et al. Universal recovery behavior of negative bias temperature instability [PMOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.
[6] X. Federspiel,et al. HCI/BTI coupled model: The path for accurate and predictive reliability simulations , 2014, 2014 IEEE International Reliability Physics Symposium.
[7] Sangwoo Pae,et al. Frequency and recovery effects in high-κ BTI degradation , 2009, 2009 IEEE International Reliability Physics Symposium.
[8] M. Agostinelli,et al. Transistor aging and reliability in 14nm tri-gate technology , 2015, 2015 IEEE International Reliability Physics Symposium.
[9] S. Ramey,et al. BTI recovery in 22nm tri-gate technology , 2014, 2014 IEEE International Reliability Physics Symposium.
[10] C. Hu. Lucky-electron model of channel hot electron emission , 1979, 1979 International Electron Devices Meeting.
[11] J. H. Chen,et al. High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme , 2010, 2010 International Electron Devices Meeting.
[12] Mark Y. Liu,et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.
[13] S. Natarajan,et al. Self-heat reliability considerations on Intel's 22nm Tri-Gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[14] R. Degraeve,et al. Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.
[15] C. Auth,et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).
[16] Mark Y. Liu,et al. Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology , 2010, 2010 IEEE International Reliability Physics Symposium.
[17] N. Horiguchi,et al. Effects of gate process on NBTI characteristics of TiN gate FinFET , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).
[18] Naoto Horiguchi,et al. Off-state stress degradation mechanism on advanced p-MOSFETs , 2015, 2015 International Conference on IC Design & Technology (ICICDT).
[19] Steven W. Mittl,et al. Self-heating and its implications on hot carrier reliability evaluations , 2015, 2015 IEEE International Reliability Physics Symposium.
[20] S. Ramey,et al. Transistor reliability variation correlation to threshold voltage , 2015, 2015 IEEE International Reliability Physics Symposium.
[21] T. Grasser,et al. The Universality of NBTI Relaxation and its Implications for Modeling and Characterization , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.
[22] M. Choe,et al. Technology scaling on High-K & Metal-Gate FinFET BTI reliability , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[23] A. Rahman,et al. Intrinsic transistor reliability improvements from 22nm tri-gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[24] R. Kotlyar,et al. High performance Hi-K + metal gate strain enhanced transistors on (110) silicon , 2008, 2008 IEEE International Electron Devices Meeting.
[25] B. Kaczer,et al. Reliability issues in MuGFET nanodevices , 2008, 2008 IEEE International Reliability Physics Symposium.