A single-chip U-interface transceiver for ISDN

The authors discuss system and implementation aspects of a 144 kbit/s one-chip U-transceiver based on echo-cancellation techniques using the MMS43 line code and a Barker synchronization word for bit and frame timing, and including a 1-kb/s transparent channel for maintenance purposes. The LSI is realized by a 2-/spl mu/m CMOS, double-metal, double-poly technology shrinkable to a 1.5-/spl mu/m technology and packaged in a 28-pin DIL (dual in-line) package.

[1]  Danny Sallaerts,et al.  Integrated Full-Digital U-Interface Circuit for ISDN Subscriber Loops , 1986, IEEE J. Sel. Areas Commun..

[2]  P.R. Gray,et al.  MOS operational amplifier design-a tutorial overview , 1982, IEEE Journal of Solid-State Circuits.

[3]  K. Shenoi,et al.  Design Methodology for ΣΔM , 1983, IEEE Trans. Commun..

[4]  H. T. Kung.  Let's Design Algorithms for VLSI Systems , 1979 .